2MS/s SPLIT SAR ADC USING 0.18um CMOS TECHNOLOGY

This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter (DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is 96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimized architecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy of the components, which improves the performance of SAR ADC. Comparator constructed from resistances, capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.